This invention relates to integrated circuits such as programmable logic device integrated circuits, and more particularly, to accurate delay chain circuitry for integrated circuits.
Integrated circuits such as programmable logic devices often contain delay chain circuits for use in phase-locked loops, delay-locked loops, programmable delay circuits, input and output circuits, and other circuitry. A typical delay chain has a number of series-connected inverters. When a signal is applied to the input of the chain, it propagates though the inverters. Each inverter contributes a delay. The total delay of the chain is equal to the sum of the delays contributed by each inverter in the chain.
The accuracy of delay chain circuits is often critical for satisfactory device performance. If a delay chain is too fast or too slow, signals passing through the chain will not be delayed by the desired amount and the integrated circuit may not function properly.
Conventional programmable logic device delay chain circuits are susceptible to changes induced by temperature fluctuations and process variations. These sources of error reduce accuracy and make it difficult or impossible to use delay chain circuits effectively in many applications.
It would be desirable to be able to provide ways in which to increase delay chain circuit accuracy on integrated circuits such as programmable logic devices.